View RDA5802H_7668824.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

cop y ri gh t ? rd a mi croelec t ro n ics inc. 20 06. a l l righ t s are rese r v e d . the information contained herein is the exclus ive property of rda and shall not be distributed, reproduced, or disclosed in who le or in part without prior written permission of rda. RDA5802H s ingle -c hip b roadcast fm r adio t uner rev.1.1?aug.2010 1 general description the RDA5802H is a new generation single-chip broadcast fm stereo radio tuner with fully integrated synthesizer, if selectivity and mpx decoder. the tuner uses the cmos process, support multi-interface and require the least external component. the package size is 4x4mm and is completely adjustment-free. all these make it very suitable for portable devices. the RDA5802H has a powerful low-if digital audio processor, this make it have optimum sound quality with varying reception conditions. the RDA5802H can be tuned to the worldwide frequency band, even support frequency range 50~65mhz. 1.1 features ? cmos single-chip full y-integrated fm tuner ? low power consumption ? total current consumption lower than 21ma at 3.0v power supply when under normal situation ? support worldwide frequency band ? 50 -108 mhz ? support flexible channel spacing mode ? 100khz, 200khz, 50khz and 25khz ? digital low-if tuner ? image-reject down-converter ? high performance a/d converter ? if selectivity performed internally ? fully integrated digi tal frequency synthesizer ? fully integrated on-chip rf and if vco ? fully integrated on-chip loop filter ? autonomous search tuning ? support 32.768khz crystal oscillator ? digital auto gain control (agc) ? digital adaptive noise cancellation ? mono/stereo switch ? soft mute ? high cut ? programmable de-emphasis (50/75 ? s) ? receive signal strength indicator (rssi) and snr ? bass boost ? volume control and mute ? i 2 s digital output interface ? line-level analog output voltage ? 32.768 khz 12m,24m,13m,26 m ,1 9.2m,38 . 4mh z reference clock ? 2-wire and 3-wire serial control bus interface ? directly support 32 ? resistance loading ? integrated ldo regulator ? 1.8 to 5.5 v operation voltage ? 4x4mm 24 pin qfn package figure 1-1. RDA5802H top view http://
rda mic r oelec tronics , inc . rda5 802 h f m t uner v1.1 1.2 applications ? cellular handsets ? mp3, mp4 players ? portable radios ? pdas, notebook the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be distributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 2 of 23
rda mic r oelec tronics , inc . rda5 802 h f m t uner v1.1 2 table of contents 1 ? general desc ription ............................................................................................................................... ..... 1 ? 1.1 ? features ............................................................................................................................... .......... 1 ? 1.2 ? a pplica tio ns ............................................................................................................................... ..... 2 ? 2 ? t a ble of cont ents ............................................................................................................................... .......... 2 ? 3 ? functional d e scription ............................................................................................................................... .3 ? 3. 1 ? fm receiver ............................................................................................................................... ... 3 ? 3. 2 ? sy nthesi zer1 ............................................................................................................................... ... 3 ? 3. 3 ? de lta -sig m a synt he siz e r ................................................................................................................... 4 ? 3. 4 ? power supply ............................................................................................................................... .4 ? 3. 5 ? reset a nd c ontr o l in terfac e sel ect ............................................................................................. 4 ? 3. 6 ? control interf ace ........................................................................................................................... 4 ? 3. 7 ? i 2 s au d i o da ta in te rfa c e ............................................................................................................... 4 ? 3. 8 ? gpio ou tp u t s ............................................................................................................................... .4 ? 4 ? electr i c a l ch aracteristi c s ........................................................................................................................... 5 ? 5 ? receiver characte ristics ............................................................................................................................. 6 ? 6 ? serial interface ............................................................................................................................... ............. 7 ? 6. 1 ? three-wire int e rface t i m i ng ......................................................................................................... 7 ? 6. 2 ? i 2 c interface t i m i ng ...................................................................................................................... 8 ? 7 ? reg i ster definitio n ............................................................................................................................... ....... 9 ? 8 pins description ............................................................................................................................... .......... 13 ? 9 ? a pplication d i agr am ............................................................................................................................... .. 15 ? 9.1 ? a udi o lo ad in g res ista n ce lar g er tha n 3 2 & t cx o a ppli cat io n: ......................................... 15 ? 9.1 . 1 ? bill of mat e ri als: ......................................................................................................................... 15 ? 9.2 ? a udi o lo ad in g res ista n ce low er th an 3 2 & dcxo ap p l ication : ........................................ 16 ? 9.2 . 1 ? bill of mat e ri als: ......................................................................................................................... 16 ? 10 ? package physical dimensi o n .................................................................................................................... 17 ? 11 ? pcb land p a ttern ............................................................................................................................... ...... 18 ? 12 ? c h ange list ............................................................................................................................... ................. 21 ? 13 ? no tes ............................................................................................................................... ........................ 21 ? 14 ? contact information ............................................................................................................................... .. 22 ? the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be distributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 2 of 23
rda mic r oelec tronics , inc . rda5 802 h f m t uner v1.1 3 functional description i adc l dac r dac q adc + - aud io d sp co re di g i ta l filter mpx de coder stereo/mono audio vco synthesizer1 gpio interface bus rssi vio sd io sc lk se n rs t mcu gp io RDA5802H lo ut rou t ln an ln ap rc lk 2.7-5.5 v 32 . 7 68 kh z vd d ldo limiter ? -synthesizer lna i pga q pga figure 3-1. RDA5802H fm tuner block diagram 3.1 fm receiver the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be distributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 3 of 23 the receiver use s a di git a l low-if archite c ture th at avoids the dif f iculties a s soci ated wi th direct conve r si on while delive r i ng lowe r sol ution co st and redu ce s compl e xity , and integ r a t es a lo w noise ampli f ier (l na) supp orting the fm broa dcast b a nd (5 0 to 10 8mhz), a m ulti-pha se image -rej ect mixer array , a pro gra mm able gai n control (pga ), a high re solution anal o g -to-digit a l conve r ters (adcs), an a udio dsp a n d a high - fidelity digit a l-to-anal og con v erters (dacs). the lna has differential input ports (lnap and lnan) and supports any input port by set according registers bits (lna_port_sel[1:0]). it default input common mode voltage is gnd. the limiter prevents overloading and limits the amount of intermodulation products created by strong adjacent channels. the multi-phase mixer array down converts the lna output differential rf signal to low-if, it also has image-reject function and harmonic tones rejection. the pga a m plifies the mix e r outp u t if signal an d then digitized with adcs. the dsp core finishes the channel selection, fm demodulation, stereo mpx decoder and output audio signal. the mpx decoder can autonomous switch from stereo to mono to limit the output noise. the dacs convert digital audio signal to analog and change the volume at same time. the dacs has low-pass feature and -3db frequency is about 30 khz. 3.2 synthesizer1 the frequency synthesizer 1 generates the local oscillator signal which divi de to multi-phase, then be used to downconvert the rf input to a constant low intermediate frequency (if). the synthesizer reference clock is 32.768 khz. the synthesizer frequency is defined by bits chan[9:0] with the range from 50mhz to 108mhz.
rda mic r oelec tronics , inc . rda5 802 h f m t uner v1.1 3.3 delta-sigma synthesizer the de lta-si g m a sy nthesiz e r ge nerat es t h e c onst an t clock s i gnal to adcs and d s p . 3.4 power supply the RDA5802H integrated one ldo which supplies power to the chip. the external supply voltage range is 1.8-5.5 v. 3.5 reset and control interface select the rda580 2h is reset itself when vio is power up. and also support soft reset by trigger 02h bit1 from 0 to 1. the control interface is select by mode pin. the mode pin is low, i2c interface is select. the mode pin is set to vio, spi interface is select. 3.6 control interface the RDA5802H supports three- wire and i 2 c control interface. user could select either of them to program the chip. the three - wire interfa c e is a st andard spi interface. it inclu d e s three pins: sen, sclk and sdio. each registe r write i s 25-bit long, including 4-bit high re gister add re ss, a r/w bit, 4-bit low regi ster a ddress, and 16 -bit dat a (msb is the first bit). rda580 2h sam p les comman d byte and d a t a at posed ge o f sclk. each registe r re ad is also 25-bit long, including 4-bit high register address, a r/w bit, 4-bit low register address, and 16-bit data (msb is the first bit) from RDA5802H. the turn around cycle between command byte from mcu and data from RDA5802H is a half cycle. RDA5802H samples command byte at posedge of sclk, and output data also at posedge of sclk. the i 2 c int e rface is compliant to i 2 c bus s pecification 2.1. it include s two pins: sclk and sdio. a i 2 c interface tran sfer be gin s with st ar t con d ition, a comman d byte and dat a bytes, each byte has a fol l owe d ack (or na ck) bit, and end s with st op co ndition. the comman d byte include s a 7-bit chi p address (00 1 0000 b) and a r/ w bit. the ack (o r nack) is always sent o u t by re ceive r . whe n in write tran sfer , d a t a bytes i s written o u t from mcu, a nd when in read tran sfer , dat a bytes is rea d out from rda 580 2h. the r e is no visible register address in i 2 c interface transfers. the i 2 c interface has a fixed start register address (0x02h for write transfer and 0x0ah for read transfer), and an internal incremental address counter. if register address meets the end of r egister file, 0x3ah, register address will wrap back to 0x00h. for write transfer, mcu programs registers from register 0x02h high byte, then register 0x02h low byte, then register 0x03h high byte, till the last register. RDA5802H always gives out ack after every byte, and mcu gives out stop condition when register programming is finished. for read transfer, after command byte from mcu, RDA5802H sends out register 0x0ah high byte, then register 0x0ah low byte, then register 0x0bh high byte, till receives nack from mcu. mcu gives out ack for data bytes besides last data byte. mcu gives out nack for last data byte, and then RDA5802H will return the bus to mcu, and mcu will give out stop condition. details refer to RDA5802H programming guide . 3.7 i 2 s audio data interface the rda580 2h su ppo rt s i 2 s (inter_ic sound bus) audio interfa c e. the interface is fully compli ant with i 2 s bus specifi c ation. whe n setting i2sen bit high, RDA5802H will output sck, ws, sd signal s from gpio3, gpio1, gpio2 as i 2 s m aster and transmitter , the sampl e rate is 48kbp s 44.1kbp s,32 kbp s ?.. rda5802 h al so suppo rt as i 2 s slaver mode and tran smitter , the sample rate is less than 1 00kbp s. det ails refer to RDA5802H programming guide . 3.8 gpio outputs the RDA5802H has three gpios. the function of gpios could programmed with bits gpio1[1:0], gpio2[1:0], gpio3[1:0] and i2sen. if i2sen is s e t to low , gpio pins c ould be prog ram m ed to output low or hig h or hig h-z, or be prog ram m ed to output interru pt a nd ste r eo indicator with bit s gpio1[1:0], gpio2[1:0], gpio3[1:0]. gpio2 coul d be progra mmed to output a low interrupt (inte rru pt will be gene rated only with inte rrupt en able bi t stcien is set to high) whe n see k /tu ne pro c e s s complete s. gpio3 could be pro g ramm ed to output stereo indi cato r bit st . constant low, high or high-z functionality is available regardless of the state of vdd supplies or the enable bit. the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be distributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 4 of 23
rda mic r oelec tronics , inc . rda5 802 h f m t uner v1.1 sck msb sd ws 1 sck left channel lsb msb 1 sck right channel lsb figure 3-2. i2s digital audio format 4 electrical characteristics table 4-1 dc electrical specificati on (recommended operation conditions): symbol description min typ max unit vdd supply voltage 1.8 3.3 5.5 v vio interface supply voltage 1.0 - 3.6 v t amb ambient temperature -20 27 +70 v il cmos low level input voltage 0 0.3*vio v v ih cmos high level input voltage 0.7*vio vio v v th cmos threshold voltage 0.5*vio v table 4-2 dc electrical specificat ion (absolute maximum ratings): symbol description min typ max unit vio interface supply voltage -0.5 +3.6 v t amb ambient temperature -40 +90 c i in input current (1) -10 +10 ma v in input voltage (1) -0.3 vio+0.3 v v lna lna fm input level +10 dbm notes: 1. for pin: sclk, sdio, sen, mode table 4-3 power consumption specification (vdd =3.3 v, t a = 25 , unless otherwise specified) symbol description condition typ unit i vdd supply current (1) enable=1 21 ma i vdd supply current (2) enable=1 23 ma i vio interface sup p l y curr ent sclk and rclk active 60 ? a i pd powerdown current enable=0 5 ? a i vio interface powerdown current enable=0 25 ? a notes: 1. for strong input signal condition 2. for weak input signal condition the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be distributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 5 of 23
rda mic r oelec tronics , inc . rda5 802 h f m t uner v1.1 5 receiver characteristics table 5-1 receiver characteristics (vdd = 3 v, t a = 25 c, unless otherwise specified) symbol parameter conditions min typ max unit general specifications f in fm input frequency range adjust band register 50 108 mhz 50mhz - 1.5 - 65mhz - 1.5 - 88mhz - 1.2 1.5 98mhz - 1.2 1.5 v rf sensitivity 1,2,3 s/n=26db 108mhz - 1.3 1.5 ? v emf ip3 in input ip3 4 agcd=1 80 - - db ? v am am suppression 1,2 m=0.3 40 - - db s 200 adjacent channel selectivity 200khz 50 70 - db s 400 400khz selectivity 400khz 60 85 - db v afl ; v afr audio l/r output voltage 1,2 (pins lout and rout) volume [3:0] =1111 - 420 - mv mono 2 55 57 - s/n maximum signal to noise ratio 1 ,2,3,5 stereo 6 53 55 - db scs stereo channel separation 35 - - db r l audio output loading resistance single-ended 32 - - r load =1k - 0.15 0.2 thd audio total harmonic distortion 1,3,6 volum e [3:0] =1111 r load =32 - 0.2 - % aoi audio output l/r imbalance 1,6 - - 0.05 db r mute mute attenuation ratio 1 volume[3:0]=0000 60 - - db low freq 9 - 100 - bw audio audio response 1 1khz= 0db 3 db point high freq - 14 - hz pins lnan, lnap, lout, rout and nc(22,23) v com_rfin pins lnan/lnap input common mode voltage 0 v v com audi o output common m o d e voltage 8 1.0 1.05 1.1 v v com_nc pins nc (22, 23) common mode voltage floating v ! the nc(22, 23) pins should be left floating. notes: 1. f in =65 to 108mhz; f mod =1khz; de-emphasis=75 ? s; mono=1; l=r unless noted otherwise; 2. ? f=22.5khz; 3. b af = 300hz to 15khz, rbw <=10hz; 4. |f 2 -f 1 |>1mhz, f 0 =2xf 1 -f 2 , agc disable, f in =76 to 108mhz; 5. p rf =60 db u v ; 6 . ? f = 7 5 k h z , f p i l o t = 1 0 % 7 . me a s u re d a t v em f = 1 m v , f rf = 65 t o 108 mhz 8. at lout and ro u t pins 9. adjus t able the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be distributed, rep r od uced, or disclose d in w h o le or i n p art w i thout prior written per mission of rda. page 6 of 23
rda mic r oelec tronics , inc . rda5 802 h f m t uner v1.1 6 serial interface 6.1 three-wire interface timing table 6-1 three-wire interface timing characteristics (vdd = 1.8 to 5.5 v, t a = -25 to 85 c, unless otherwise specified) parameter symbol test condition min typ max unit sclk cycle time t clk 35 ns sclk rise time t r 50 ns sclk fall time t f 50 ns sclk high time t hi 10 ns sclk low time t lo 10 ns sdio input, sen to sclk setup t s 10 - - ns sdio input, to sclk hold t h 10 - - ns sclk to sdio output valid t cdv read 2 - 10 ns sen to sdio output high z t sdz read 2 - 10 ns digital input pin capacitance 5 pf figure 6-1. three-wire interface write timing diagram figure 6-2. three-wire interface read timing diagram the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be distributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 7 of 23
rda mic r oelec tronics , inc . rda5 802 h f m t uner v1.1 6.2 i 2 c interface timing table 6-2 i 2 c interface timing characteristics (vdd = 1.8 to 5.5 v, t a = -25 to 85 c, unless otherwise specified) parameter symbol test condition min typ max unit sclk frequency f scl 0 - 400 khz sclk high time t high 0.6 - - ? s sclk low time t low 1.3 - - ? s setup time for start condition t su:sta 0.6 - - ? s hold time for start condition t hd:sta 0.6 - - ? s setup time for stop condition t su:sto 0.6 - - ? s sdio input to sclk setup t su:dat 100 - - ns sdio input to sclk hold t hd:dat 0 - 900 ns stop to start time t buf 1.3 - - ? s sdio output fall time t f:out 20+0.1c b - 250 ns sdio input, sclk rise/fall time t r:in / t f:in 20+0.1c b - 300 ns input spike suppression t sp - - 50 ns sclk, sdio capacitive loading c b - - 50 pf digital input pin capacitance 5 pf figure 6-3. i 2 c interface write timing diagram figure 6-4. i 2 c interface read timing diagram the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be distributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 8 of 23
rda mic r oelec tronics , inc . rda5 802 h f m t uner v1.1 7 register definition reg bits name function default 00h 15:8 chipid[7:0] chip id. 0x58 02h 15 dhiz audio output high-z disable. 0 = high impedance; 1 = normal operation 0 14 dmute mute disable. 0 = mute; 1 = normal operation 0 13 mono mono select. 0 = stereo; 1 = force mono 0 12 bass bass boost. 0 = disabled; 1 = bass boost enabled 0 11 rclk non-calibrate mode 0=rclk clock is always supply 1=rclk clock is not always supply when fm w ork ( when 1, RDA5802H can?t directly support -20 ~70 temperature. only suppory 20 temperature swing from tune point) 0 10 rclk direct input mode 1=rclk clock use the directly input mode 0 9 seekup seek up. 0 = seek down; 1 = seek up 0 8 seek seek. 0 = disable stop seek; 1 = enable seek be gin s i n t h e directi o n sp ecifie d by seekup and e nds whe n a ch annel is fo un d, or the entire ba nd h as bee n se arched. the seek bit is set low and the stc bit is set high when the seek operation completes. 0 7 skmode seek mode 0 = wrap at the upper or lower band limit and continue seeking 1 = stop seeking at the upper or lower band limit 0 6:4 clk_mode[2:0] 000=32.768khz 001=12mhz 101=24mhz 010=13mhz 110=26mhz 011=19.2mhz 111=38.4mhz 000 1 soft_reset soft reset. if 0, not reset; if 1, reset. 0 0 enable power up enable. 0 = disabled; 1 = enabled 0 03h 15:6 chan[9:0] channel select. band = 0 0x00 the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be distributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 9 of 23
rda mic r oelec tronics , inc . rda5 802 h f m t uner v1.1 reg bits name function default frequ ency = channel spacing (khz) x chan + 87.0 mhz band = 1or 2 frequency = channel spacing (khz) x chan + 76.0 mhz band = 3 frequency = channel spacing (khz) x chan + 65.0 mhz chan is updated after a seek operation. 4 tune t u n e 0 = disable 1 = enable the tune operation begins when the tune bit is set high. the stc bit is set high when the tune operation completes. the tune bit is reset to low automatically when the tune operation completes.. 0 3:2 band[1:0] band select. 00 = 87?108 mhz (us/europe) 01 = 76?91 mhz (japan) 10 = 76?108 mhz (world wide) 11 1 = 65 ?76 mhz east euro pe or 50-65m hz 00 1:0 space[1:0] channel spacing. 00 = 100 khz 01 = 200 khz 10 = 50khz 11 = 25khz 00 04h 15 rsvd 14 stcien seek/tune complete interrupt enable. 0 = disable i n te rrupt 1 = enable interrupt settin g st cien = 1 w ill generate a lo w pulse on gpio2 when the interrupt occurs. 0 13:12 rsvd 11 de de-emphasis. 0 = 75 s; 1 = 50 s 0 10 rsvd 9 softmute_en if 1, softmute enable 1 8 afcd afc disable. if 0, afc work; if 1, afc disabled. 0 7 rsvd 6 i2s_enabled i2s bus enable if 0, disabled; if 1, enabled. 0 1 if 0x07h_bit<9> ( band )=1, 65-76mhz; =0, 50-76mhz the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be distributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 10 of 23
rda mic r oelec tronics , inc . rda5 802 h f m t uner v1.1 reg bits name function default 5:4 gpio3[1:0] general purpose i/o 3. 00 = high impedance 01 = mono/stereo indicator (st) 10 = low 11 = high 00 3:2 gpio2[1:0] general purpose i/o 2. 00 = high impedance 01 = interrupt (int) 10 = low 11 = high 00 1:0 gpio1[1:0] general purpose i/o 1. 00 = high impedance 01 = reserved 10 = low 11 = high 00 05h 15 int _mode if 0, generate 5ms interrupt; if 1, interrup t last un til read reg0ch actio n occurs. 1 14:8 seekth[6:0] 2 seek snr threshold value when seek_mode[2:0]=001 0001000 7:6 lna_port_sel[1:0] lna input port selection bit: 00: no input 01: lnan 10: lnap 11: dual port input 10 5:4 lna_icsel_bit[1:0] lna working current bit: 00=1.8ma 01=2.5ma 10=3.1 ma 11=3.8ma 00 3:0 volume[3:0] dac gain control bits (volume). 0000=min; 1111=max volume scale is logarithmic when 0000, output mute and output impedance is very large 1111 06h 14 open_mode open test register mode. 0=only open behind registers reading function 1=open behind registers writing function 0 12 i2s_mode_select if 0, master mode; if 1, slave mode. 0 7:4 i2s_ws_cnt[4:0] o n ly v a l i d in mas t er m ode 4'b1000: ws_s tep_48; 4'b0111: ws_step=44.1kbps; 4'b0110: ws_step=32kbps; 4'b0101: ws_step=24kbps; 4'b0100: ws_step=22.05kbps; 4'b0011: ws_step=16kbps; 4'b0010: ws_step=12kbps; 4'b0001: ws_step=11.025kbps; 4'b0000: ws_step=8kbps; 0000 2 this value is used when 0x20h_bit< 14:12> ( seek_mode )=001, default seek mode is audio_s nr seek mode. the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be distributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 11 of 23
rda mic r oelec tronics , inc . rda5 802 h f m t uner v1.1 reg bits name function default 0ah 14 stc seek/tune complete. 0 = not complete 1 = complete the seek/tune complete flag is set when the seek or tune operation completes. 0 13 sf seek fail. 0 = seek successful; 1 = seek failure the seek fail flag is set when the seek operation fails to find a channel with an rssi level greater than seekth[5:0] . 0 10 st stereo indicator. 0 = mono; 1 = stereo stereo indication is available on gpio3 by setting gpio1[1:0] =01. 1 9:0 readchan[9:0] read channel. band = 0 frequency = channel spacing (khz) x readchan[9:0]+ 87.0 mhz band = 1 or 2 frequency = channel spacing (khz) x readchan[9:0]+ 76.0 mhz band = 3 frequency = channel spacing (khz) x readchan[9:0]+ 65.0 mhz re a d ch a n [9 :0 ] is up d a te d af ter a tu ne or seek o p erati on. 8?h00 0bh 15:9 rssi[6:0] rssi. 000000 = min 111111 = max rssi scale is logarithmic. 0 8 fm true 1 = the current channel is a station 0 = the current channel is not a station 0 7 fm_ready 1=ready 0=not ready 0 the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be distributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 12 of 23
rda mic r oelec tronics , inc . rda5 802 h f m t uner v1.1 8 pins description 2 3 4 5 6 1 7 17 16 15 14 13 18 8 9 10 11 12 24 23 22 21 20 19 gn d pad gnd rf gn d l nap gnd rd a5 8 0 2h vdd gn d lo u t gn d l nan ro ut gn d vd d mode se n sclk sd i o rc lk vi o gn d nc nc gpi o 1 gp io2 gp io3 figure 8-1. rda580 2h top view table 8-1 RDA5802H pins description symbol pin description gnd 1,5,6,14,17,24 ground. connect to ground plane on pcb lnan,lnap 2,4 lna input port. for sing le-ended inp ut, lnan should be connected to rfgnd rfgnd 3 lna ground. connect to ground plane on pcb mode 7 control interface sele ct the mode pin is low ,i 2c interface is sele ct. the mode pin is set to vio, spi interface is select. sen 8 latch enable (active low) input for serial control bus sclk 9 clock input for serial control bus sdio 10 data input/output for serial control bus rclk 11 32.768khz crystal oscillator and reference clock input vio 12 power supply for i/o vdd 14/18 power supply rout,lout 15,16 right/left audio output gpio1,gpio2,gpio3 19,20,21 general purpose input/output nc 22,23 no connect the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be distributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 13 of 23
rda mic r oelec tronics , inc . rda5 802 h f m t uner v1.1 table 8-2 internal pin configuration symbol pin description lnan/lnap 2/4 rload rclk 11 rclk 5m 20pf 6pf inv 5m 0x02h_bit<10> vi o =1 =0 sclk/sdio 9/10 47k s in s out mn1 sdio\sclk gpio1/gpio2/gpio3 19/20/21 gpio 1 \2 \3 in out the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be distributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 14 of 23
rda mic r oelec tronics , inc . rda5 802 h f m t uner v1.1 9 application diagram 9.1 audio loading resistance larger than 32 ? & tcxo application: 7 19 notes: 1. j1: common 32 ? resistance headphone; 2. u1: RDA5802H chip; 3. v1: analog and digital power supply (1.8~5.5v); 4. fm choke (l3 and c3) for audio common and lna input common; 5. pins nc(22, 23), should be leaved floating; 6.i2c bus-wire mode; 6. place c6 close to 5802h pin. figure 9-1. RDA5802H fm tuner application diagram (tcxo application) 9.1.1 bill of materials: component value description supplier u1 RDA5802H broadcast fm radio tuner rda j1 common 32 ? resistance headphone l3/c3 100nh/24pf lc chock for lna input murata c4,c5 125f audio ac couple capacitors murata c6 22nf power supply bypass capacitor murata f1/f2 1.5k@100mhz fm band ferrite murata the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be distributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 15 of 23
rda mic r oelec tronics , inc . rda5 802 h f m t uner v1.1 9.2 audio loading resistance lower than 32 ? & dcxo application: 1 7 13 19 j1 sclk sd i o v i o v1 l 3 100nh c3 24p f c4 125 uf c5 125 uf c6 24nf f1 1 . 5k@100mh z f2 1.5k@100mhz notes: 1. j1: common 32 ? resistance headphone 2. u1: RDA5802H chip 3. v1: analog and digital power supply (1.8~5.5v) 5. pins nc(22, 23),should be leaved floating; 6.set mode to select control interface(gnd?i2c,vio?spi); 7. place c6 close to 5802h pin figure 9-2. RDA5802H fm tuner applicati on diagram (32.768k crystal,i2c bus mode) 9.2.1 bill of materials: component value description supplier u1 RDA5802H broadcast fm radio tuner rda j1 audio amplifier c4/c5 125uf audio ac couple capacitors murata l3/c3 100nh/24pf lc chock for lna input murata c6 24nf power supply bypass capacitor murata f1/f2 1.5k@100mhz fm band ferrite murata the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be distributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 16 of 23
rda mic r oelec tronics , inc . rda5 802 h f m t uner v1.1 10 package physical dimension figure 10-1 illustrates the package details for the RDA5802H. the package is lead-free and rohs-compliant. min nom max d 4.00 bsc e 4.00 bsc d2 2.60 2.70 2.80 e2 2.60 2.70 2.80 e 0.50 bsc l 0.30 0.40 0.50 b 0.18 0.25 0.30 a 0.80 0.90 1.00 a1 0.00 0.02 0.05 a3 0.20 ref figure 10-2. 24-pin 4x4 quad flat no-lead (qfn) the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be distributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 17 of 23
rda mic r oelec tronics , inc . rda5 802 h f m t uner v1.1 11 pcb land pattern figure 18.classificati on reflow profile profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (t smax to t p ) 3 o c/second max. 3 o c/second max. preheat -temperature min (t smin ) -temperature max (t smax ) -time (t smin to t smax ) 100 o c 100 o c 60-120 seconds 150 o c 200 o c 60-180 seconds time maintained above: -temperature (t l ) -time (t l ) 183 o c 60-150seconds 217 o c 60-150 seconds peak /classification temperature(t p ) see table-ii see table-iii time within 5 o c of actu al peak temperature (t p ) 10-30 seconds 20-40 seconds ramp-down rate 6 o c/second max. 6 o c/seconds max. time 25 o c to peak temperature 6 minutes max. 8 minutes max. table-i classification reflow profiles the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be distributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 18 of 23
rda mic r oelec tronics , inc . rda5 802 h f m t uner v1.1 package thickness volume mm 3 <350 volume mm 3 350 2.5mm 240 + 0/-5 o c 225 + 0/-5 o c 2.5mm 225 + 0/-5 o c 225 + 0/-5 o c table ? ii snpb eutectic process ? package peak reflow temperatures package thickness volume mm 3 350 volume mm 3 350-2000 volume mm 3 2000 1.6mm 260 + 0 o c * 260 + 0 o c * 260 + 0 o c * 1.6mm ? 2.5mm 260 + 0 o c * 250 + 0 o c * 245 + 0 o c * 2.5mm 250 + 0 o c * 245 + 0 o c * 245 + 0 o c * * tolerance : the device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperatur e(this mean peak reflow temperature + 0 o c. for example 260+ 0 o c ) at the rated msl level. table ? iii pb-free proces s ? package classification reflow temperatures note 1: all temperature refer topside of the package. measured on the package body surface. note 2: the profiling tolerance is + 0 o c, - x o c (based on machine variation capability)whatever is r equired to control the p r ofile proce ss but at n o time will i t exceed - 5 o c. the producer assures proce ss compatibility at the pe ak reflow pr ofile temperatures defin ed in table ?iii. note 3: package volume excludes external term inals(balls, bumps, lands, leads) and/or non integral heat sinks. note 4: the maximum component temperature reached during reflow depends on package the thickness and volume. the use of convection reflow processes reduces the thermal gradients between packages. however, thermal gradients due to differences in thermal mass of smd package may sill exist. note 5: components intended for use in a ?lead-free? assembly process shall be evaluated using the ?lead free? classification temperat ures and profiles defined in table-i ii iii whether or not lead free. the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be distributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 19 of 23
rda mic r oelec tronics , inc . rda5 802 h f m t uner v1.1 rohs compliant the product does not contain lead, mercury, cadmium, hexavalent chromium, polybrominated biphenyls (pbb) or polybrominated diphenyl ethers (pbde), an d are therefore consider ed rohs compliant. esd sensitivity integrated circuits are esd sensitive and can be damaged by static electricity. proper esd techniques should be used when handling these devices. the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be distributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 20 of 23
rda mic r oelec tronics , inc . rda5 802 h f m t uner v1.1 12 change list rev date auther change description v1.0 2009-03-03 chun zhao, yanan liu original draft. 13 notes 1: ???????? mo de se n sclk sdio sc l k vio 7 8 9 sd i o 10 sen mo d e se n sclk sdio sclk 7 8 9 sd i o 10 ? i2c ? ? s p i ? ? the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be distributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 21 of 23
rda mic r oelec tronics , inc . rda5 802 h f m t uner v1.1 14 contact information rda microelectronics (shanghai), inc. suite 1108 block a, e-wing center, 113 zhichun road haidian district, beijing tel: 86-10-62635360 fax: 86-10-82612663 postal code: 100086 suite 302 building 2, 690 bibo road pudong district, shanghai tel: 86-21-50271108 fax: 86-21-50271099 post al code: 201203 copyright ? rda microelectronics inc. 2006. all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the infor m ation cont ained her ein is the exclus ive propert y of rda a nd shall not be distributed, rep r od uced, or disclose d in w h o le or i n part without prior written permission of rda. page 22 of 23

▲Up To Search▲

Price & Availability of RDA5802H

	To Download RDA5802H Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .